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january 2011 doc id 18211 rev 2 1/29 29 ALTAIR04-900 off-line all-primary-sensing switching regulator features primary side constant voltage operations with no optocoupler adjustable and main-independent maximum output current for safe operations during overload/short circuit conditions 900 v avalanche rugged internal power section quasi-resonant valley switching operation low standby consumption overcurrent protection against transformer saturation and secondary diode short circuit so16 package applications smps for energy metering auxiliary power supplie s for 3-phases input industrial systems ac-dc adapters description ALTAIR04-900 is a high-voltage all-primary- sensing switcher intended for operating directly from the rectified main s with minimum external parts. it combines a high-performance low- voltage pwm controller chip and a 900 v avalanche-rugged power section in the same package. so16n figure 1. block diagram ? 3.3 v zcd/f b i ff sta rt er sourc e tur n - o n logi c +vi n +v out is ta r t -u p internal supply bu s vref in te r n . suppl y bu s drain blanking time le b vc c ir e f 2.5 v r s q comp - + - + + - s/h de mag logic gnd s r q ir ef r p rot ection & fe edforward lo g i c pr o t i ff vc - + 1 v s r q uv l o uv lo pr o t r ff su pp l y & uv l o rfb rz cd rsens e rcomp ccomp cr e f 3.3 v zcd/f b i ff sta rt er sta rt er sourc e tur n - o n logi c +vi n +v out is ta r t -u p internal supply bu s vref in te r n . suppl y bu s drain blanking time blanking time le b le b vc c ir e f 2.5 v r s q comp - + - + - + + - + - s/h s/h de mag logic de mag logic gnd s r q s r q ir ef r p rot ection & fe edforward lo g i c p rot ection & fe edforward lo g i c pr o t i ff vc - + - + 1 v s r q s r q uv l o uv lo pr o t r ff su pp l y & uv l o rfb rz cd rsens e rcomp ccomp cr e f www.st.com
contents ALTAIR04-900 2/29 doc id 18211 rev 2 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 zero current detection and triggering block . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 voltage feedforward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 18 5.8 soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 hiccup mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.10 layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 test board: evaluation data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 test board: main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ALTAIR04-900 device description doc id 18211 rev 2 3/29 1 device description the device combines two silicon in the same package: a low volta ge pwm controller and a 900 v avalanche rugged power section. the controller is a current-mode specifically designed for off-line quasi-resonant flyback converters. the device is capable of providing constant output voltage using all primary sensing feedback. this eliminates the need for the optocoupler, the secondary voltage reference, as well as the current sensor, still ma intaining quite accurate regula tion. also, it is possible to set the maximum deliverable output current, thus increasing the end-product's safety and reliability during fault events. quasi-resonant operation is guaranteed by means of a transformer demagnetization sensing input that turns on the power section. the same input serves also the output voltage monitor, to perform cv regulation, and the input voltage monitor, to achieve mains- independent maximum deliverable output current (line voltage feedforward). the maximum switching frequency is top-limited below 166 khz, so that at medium-light load a special function automatically lowers the operating frequen cy still maintaining the valley switching operation. at very light load, the device enters a controlled burst-mode operation that, along with the built-in high-voltage start-up circuit and the low operating current, helps minimize the standby power. although an auxiliary winding is required in the transforme r to correctly perform cv/cc regulation, the chip is able to power itself dire ctly from the rectified mains. this is useful especially during cc regulation, where the flyback voltage generated by the winding drops below uvlo threshold. however, if ultra-low no-load input consumption is required to comply with the most stringent energy-saving recommendations, then the device needs to be powered via the auxiliary winding. in addition to these functions that optimize power handling under different operating conditions, the device offers protection featur es that considerably increase end-product's safety and reliability: auxiliary winding discon nection - or brownout - detection and shorted secondary rectifier - or transformer's saturation - detection. all of them are auto restart mode.
pin connection ALTAIR04-900 4/29 doc id 18211 rev 2 2 pin connection figure 2. pin connection (top view) note: the copper area for heat dissipation has to be designed under the drain pins n.a. n.a. source drain source gnd iref zcd/fb comp vcc drain drain drain n.a. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n.c. n.a. n.a. source drain source gnd iref zcd/fb comp vcc drain drain drain drain drain n.a. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n.c. n.a. table 1. pin functions n. name function 1, 2 source power section source and input to the pwm co mparator. the current flowing in the mosfet is sensed through a resistor connected between the pin and gnd. the resulting voltage is compared with an internal reference (0.75v max. ) to determine mosfet?s turn-off. the pin is equipped with 250 ns blanking time after the gate-drive output goes high for improved noise immunity. if a second comparison level located at 1v is exceeded the ic is stopped and restarted after vcc has dropped below 5v. 3vcc supply voltage of the device. an electrolyt ic capacitor, connected between this pin and ground, is initially charged by the internal high- voltage start-up generator; when the device is running the same generator keeps it charged in case the voltage supplied by the auxiliary winding is not sufficient. this feature is disabled in case a protection is tripped. sometimes a small bypass capacitor (0.1 f typ.) to gnd mi ght be useful to get a clean bias voltage for the signal part of the ic. 4gnd ground. current return for both the signal part of the ic and the gate drive. all of the ground connections of the bias components should be tied to a trace going to this pin and kept separate from any pulsed current return. 5iref cc regulation loop reference voltage. an external capacitor has to be connected between this pin and gnd. an internal circuit develops a voltage on this capacitor that is used as the reference for the mosfet?s peak drain cu rrent during cc regulation. the voltage is automatically adjusted to keep the average output current constant.
ALTAIR04-900 pin connection doc id 18211 rev 2 5/29 6 zcd/fb transformer?s demagnetization sensing for q uasi-resonant operation. input/output voltage monitor. a negative-going edge triggers mosfet?s turn-on. the current sourced by the pin during on-time is monitored to get an image of t he input voltage to the converter, in order to compensate the internal delay of the current sensing circuit and achieve a cc regulation independent of the mains voltage. if this current does not exceed 50a, either a floating pin or an abnormally low input voltage is assumed, the device is stopped and restarted after vcc has dropped below 5v. still, the pin voltage is sampled-and-held right at the end of transformer?s demagnetization to get an accurate image of the output volt age to be fed to the inverting input of the internal, transconductance-type, error amplifier, whose non-inverting input is referenced to 2.5v. please note that the maximum i zcd/fb sunk/sourced current has to not exceed 2 ma (amr) in all the vin range conditions. no capacitor is allowed between the pin and the auxiliary transformer. 7comp output of the internal transconductance error amplifier. the compensation network is placed between this pin and gnd to achieve stability and good dynamic performance of the voltage control loop. 8-11 n.a not available. these pins must be left not connected 12 n.c not internally connected. provision for clearance on the pcb to meet safety requirements. 13 to 16 drain drain connection of the internal power section. the internal high-voltage start-up generator sinks current from this pin as well. pins conn ected to the internal me tal frame to facilitate heat dissipation. table 1. pin functions (continued) n. name function
maximum ratings ALTAIR04-900 6/29 doc id 18211 rev 2 3 maximum ratings 3.1 absolute maximum ratings 3.2 thermal data table 2. absolute maximum ratings symbol pin parameter value unit v ds 1,2, 13-16 drain-to-source (g round) voltage -1 to 900 v i d 1,2, 13-16 drain current 0.7 a eav 1,2, 13-16 single pulse avalanche energy (tj = 25c, i d = 0.7a) 25 mj vcc 3 supply voltage (icc < 25ma) self limiting v i zcd/fb 6 zero current detector current 2 ma vcomp 8 analog input -0.3 to 3.6 v p tot power dissipation @t a = 50c 0.9 w t j junction temperature range -25 to 150 c t stg storage temperature -55 to 150 c table 3. thermal data symbol parameter max. value unit r th j-pin thermal resistance, junction-to-pin 10 c/w r th j-amb thermal resistance, junction-to-ambient 110
ALTAIR04-900 electrical characteristics doc id 18211 rev 2 7/29 4 electrical characteristics (t j = -25 to 125 c, vcc = 14 v; unless otherwise specified) table 4. electrical characteristics symbol parameter test condition min. typ. max. unit power section v (br)dss drain-source breakdown i d < 100 a; tj = 25 c 900 v i dss off state drain current v ds = 850 v; tj = 125 c (see figure 4 and note) 80 a r ds(on) drain-source on-state resistance id=250 ma; tj = 25 c 16 19 w id=250 ma; tj = 125 c 38 c oss effective (energy-related) output capacitance (see figure 3 ) high-voltage start-up generator v start min. drain start voltage i charge < 100 a 40 50 60 v i charge vcc startup charge current v drain > v start ; vcc < vcc on tj = 25 c 45.5 7 ma v drain > v start ; vcc < vcc on +/-10% v ccrestart vcc restart voltage (vcc falling) (1) 9.5 10.5 11.5 v after protection tripping 5 supply voltage vcc operating range after turn-on 11.5 23 v vcc on turn-on threshold (1) 12 13 14 v vcc off turn-off threshold (1) 91011v v z zener voltage icc = 20 ma 23 25 27 v supply current icc start-up start-up current (see figure 5 ) 200 300 a iq quiescent current (see figure 6 )11.4ma icc operating supply current @ 50 khz (see figure 7 )1.41.7ma iq (fault) fault quiescent current during hiccup and brownout (see figure 8 ) 250 350 a start-up timer t start start timer period 100 125 175 s t restart restart timer period during burst mode 400 500 700 s zero current detector i zcdb input bias current v zcd = 0.1 to 3 v 0.1 1 a v zcdh upper clamp voltage i zcd = 1 ma 3.0 3.3 3.6 v
electrical characteristics ALTAIR04-900 8/29 doc id 18211 rev 2 v zcdl lower clamp voltage i zcd = - 1 ma -90 -60 -30 mv v zcda arming voltage positive-going edge 100 110 120 mv v zcdt triggering voltage negative-going edge 50 60 70 mv i zcdon min. source current during mosfet on-time -25 -50 -75 a t blank trigger blanking time after mosfet?s turn-off v comp 1.3v 6 s v comp = 0.9v 30 line feedforward r ff equivalent feedforward resistor i zcd = 1ma 45 transconductance error amplifier v ref voltage reference tj = 25c (1) 2.46 2.5 2.54 v tj = -25 to 125c and vcc=12v to 23v (1) 2.42 2.58 gm transconductance i comp = 10 a v comp = 1.65 v 1.3 2.2 3.2 ms gv voltage gain open loop 73 db gb gain-bandwidth product 500 khz i comp source current v zcd = 2.3v, v comp = 1.65v 70 100 a sink current v zcd = 2.7v, v comp = 1.65v 400 750 a v comph upper comp voltage v zcd = 2.3 v 2.7 v v compl lower comp voltage v zcd = 2.7 v 0.7 v v compbm burst-mode threshold 1 v hys burst-mode hysteresis 65 mv current reference v irefx maximum value v comp = v compl (1) 1.5 1.6 1.7 v g i current loop gain v comp = v comph 0.5 0.6 0.7 v cref current reference voltage 0.38 0.4 0.42 v current sense t leb leading-edge blanking 200 250 300 ns t d(h-l) delay-to-output 300 ns v csx max. clamp value dvcs/dt = 200 mv/s (1) 0.7 0.75 0.8 v v csdis hiccup-mode ocp level (1) 0.92 1 1.08 v 1. parameters tracking each other table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
ALTAIR04-900 electrical characteristics doc id 18211 rev 2 9/29 figure 3. c oss output capacitance variation figure 4. off state drain and source current test circuit note: the measured i dss is the sum between the current across the start-up resistor and the effective mosfet?s off state drain current figure 5. start-up current test circuit 0 25 50 75 100 125 150 0 100 200 300 400 500 c oss (pf) v ds (v) a iq(f ault) a idss 850 v 15v 2. 5v comp source drain vdd + - current control iref gnd fb/zcd ? 1 1.8 v a ic cstart-up 2. 5v comp source drain vdd + - current control ir ef gnd fb/zcd
electrical characteristics ALTAIR04-900 10/29 doc id 18211 rev 2 figure 6. quiescent current test circuit figure 7. operating supply current test circuit note: the circuit across the zcd pin is used for switch-on synchronization figure 8. quiescent current during fault test circuit ? 14 v a iq_meas 0. 2v 3v 33k 0.8v 10k 2.5 v comp source drain vdd + - current control iref gnd fb/zcd ? 2.8v 1.5k 2w a icc 15 v 10 10 k 10 k -5v 50 kh z 27k 220 k 5.6 15 0v 2. 5v comp source drain vdd + - current control iref gnd fb/zcd ? 14v a iq(fault) 2. 5v comp source drain vdd + - current control ir ef gnd fb/zcd
ALTAIR04-900 application information doc id 18211 rev 2 11/29 5 application information the device is an all-primary sensing switching regulator, based on quasi-resonant flyback topology. depending on converter?s load condition, the device is able to work in different modes (see figure 9 ): 1. qr mode at heavy load. quasi-resonant operation lies in synchronizing mosfet's turn-on to the transformer?s demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. then the system works close to the boundary between discontinuous (dcm) and continuous conduction (ccm) of the transformer. as a result, the switching frequency is different for different line/load conditions (see the hyperbolic-like portion of the curves in figure 9 ). minimum turn-on losses, low emi emission and safe behavior in short circuit are the main benefits of this kind of operation. 2. valley-skipping mode at medium/ light load. depending on voltage on comp pin, the device defines the maximum operating frequency of the converter. as the load is reduced mosfet?s turn-on does not any more occur on the first valley but on the second one, the third one and so on. in this way the switching frequency is no longer increased (piecewise linear portion in figure 9 ). 3. burst-mode with no or very light load. when the load is extremely light or disconnected, the converter enters a controlled on/off operation with constant peak current. decreasing the load results in frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequenc y-related losses and making it easier to comply with energy saving regulations or recommendations. being the peak current very low, no issue of audible noise arises. figure 9. multi-mode operation of ALTAIR04-900 ? 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode 0 f sw pinmax input voltage p in f osc burst-mode valley-skipping mode quasi-resonant mode
application information ALTAIR04-900 12/29 doc id 18211 rev 2 5.1 power section and gate driver the power section guarantees safe avalanche op eration within the specified energy rating as well as high dv/dt capabilit y. the power mosfet has a v (br)dss of 900 v min. and a typical r ds(on) of 16 . the gate driver is designed to supply a controlled gate current during both turn-on and turn- off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit holds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. 5.2 high voltage startup generator figure 10 shows the internal schematic of the high-voltage start-up generator (hv generator). the hv current generator is supplied through the drain pin and it is enabled only if the input bulk capacitor voltage is higher than vstart threshold, 50 v dc typically. when the hv current generator is on, the icharge current (5.5 ma typical value) is delivered to the capacitor on the v cc pin. with reference to the timing diagram of figure 10 , when power is applied to the circuit and the voltage on the input bulk capacitor is high enough, the hv generator is sufficiently biased to start operating, thus it draws about 5. 5 ma (typical) from the bulk capacitor. most of this current charges the bypass capacitor connected between the vcc pin and ground and make its voltage rise linearly. as the vcc voltage reaches the start-up threshold (13 v typ.) the chip starts operating, the internal power mosfet is enabled to switch and the hv generator is cut off by the vcc_ok signal asserted high. the ic is powered by the energy stored in the vcc capacitor. the chip is able to power itself directly from the rectified mains: when the voltage on the v cc pin falls below vcc restart (10.5v typ.), during each mosfet?s off-time the hv current generator is turned on and charges the supply capacitor until it reaches the v ccon threshold. in this way, the self-supply circuit develops a voltage high enough to sustain the operation of the device. this feature is useful especially during cc regulation, when the flyback voltage generated by the auxiliary winding alone may no t be able to keep vcc above vccrestart. at converter power-down the system loses regulation as soon as the input voltage falls below v start . this prevents converter?s restart attempts and ensures monotonic output voltage decay at system power-down.
ALTAIR04-900 application information doc id 18211 rev 2 13/29 figure 10. timing diagram: normal power-up and power-down sequences 5.3 zero current detection and triggering block the zero current detection (zcd) and triggering blocks switch on the power mosfet if a negative-going edge falling below 50 mv is applied to the zcd/fb pin. to do so, the triggering block must be previously armed by a positive-going edge exceeding 100 mv. this feature is used to detect transforme r demagnetization for qr operation, where the signal for the zcd input is obtained from th e transformer?s auxiliary winding used also to supply the ic. figure 11. zcd block, triggering block the triggering block is blanked after mosfet?s turn-off to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the zcd circuit erroneously. this blanking time is dependent on the voltage on comp pin: it is t blank = 30 s for v comp = 0.9 v, and decreases almost linearly down to t blank = 6 s for v comp = 1.3 v ? vcc drain vcc on vcc resta rt t t t t vin v sta rt i cha rg e 5.5 ma t t po wer-on power-off norma l op era tion cv mode cc mode normal operation vcc drain vcc on vcc resta rt t t t t vin v sta rt i cha rg e 5.5 ma t t po wer-on power-off norma l op era tion cv mode cc mode normal operation ? 60 m v zcd clamp b l an kin g ti me tu r n - o n logi c starter s r q leb + - aux rf b rzcd to d riv er from cc /cv block from ocp zcd/ fb 110mv
application information ALTAIR04-900 14/29 doc id 18211 rev 2 the voltage on the pin is both top and bottom lim ited by a double clamp, as illustrated in the internal diagram of the zcd block of figure 11 . the upper clamp is typically at 3.3 v, while the lower clamp is located at -60mv. the inte rface between the pin and the auxiliary winding is a resistor divider. its resistance ratio as we ll as the individual resistance values has to be properly chosen (see ? section 5.4: constant voltage operation ? and ? section 5.6: voltage feedforward block ?. please note that the maximum i zcd/fb sunk/sourced current has to not exceed 2 ma (amr) in all the vin range conditions. no capacitor is allowed between zcd pin and the auxiliary transformer. the switching frequency is top-limited below 166 khz, as the converter?s operating frequency tends to increase excessively at light load and high input voltage. a starter block is also used to start-up the system, that is, to turn on the mosfet during converter power-up, when no or a too small signal is available on the zcd pin. the starter frequency is 2 khz if comp pin be low burst mode threshold, i.e. 1 v, while it becomes 8 khz if this voltage exceed this value. after the first few cycles initiated by the starte r, as the voltage develo ped across the auxiliary winding becomes large enough to arm the zcd circuit, mosfet?s turn-on starts to be locked to transformer demagnetization, hence setting up qr operation. the starter is activated also when the ic is in cc regulation and the output voltage is not high enough to allow the zcd triggering. if the demagnetization completes ? hence a negative-going edge appears on the zcd pin ? after a time exceeding time t blank from the previous turn-on, the mosfet is turned on again, with some delay to ensure minimum voltage at turn-on. if, instead, the negative-going edge appears before t blank has elapsed, it is ignored an d only the first negative-going edge after t blank turns-on the mosfet. in this way one or more drain ringing cycles is skipped (?valley-skipping mode?, figure 12 ) and the switching frequency is prevented from exceeding 1/t blank . figure 12. drain ringing cycle skipping as the load is progressively reduced note that when the system operates in va lley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the mosfet is allowed to change with discrete steps of one ringing cycle, while the off-time needed for cycle-by-cycle energy balance may fa ll in between. thus one or more longer switching cycles is compensated by one or more shorter cycles and vice versa. however, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. ? p in = p in' ( limit condi ti on) p in = p in'' < p in' p in = p in''' < p in'' t v ds t fw t osc t v t on t v ds t osc t v ds t o sc
ALTAIR04-900 application information doc id 18211 rev 2 15/29 5.4 constant voltage operation the ic is specifically desig ned to work in primary regulation and the output voltage is sensed through a voltage partiti on of the auxiliary winding, just before the auxiliary rectifier diode. figure 13 shows the internal schematic of the constant voltage mode and the external connections. figure 13. voltage control principle: internal schematic due to the parasitic wires resistanc e, the auxiliary voltage is repr esentative of the output just when the secondary current becomes zero. for this purpose, the signal on zcd/fb pin is sampled-and-held at the end of transformer?s demagnetization to get an accurate image of the output voltage and it is compared with the error amplifier internal reference. the comp pin is used for the frequency compensation: usually, an rc network, which stabilizes the overall voltage control loop, is connected between this pin and ground. the output voltage can be defined according the formula: where n sec and n aux are the secondary an d auxiliary turn?s number respectively. the r zcd value can be defined depending on the application parameters (see ? section 5.6: voltage feedforward block ?). ? 2. 5v rzcd from rsense aux + - ea r to pwm logic s/ h rf b demag logi c + - cv c comp zcd/fb (1) r fb v ref n aux n sec -------------- v out v ref ? ? ------------------------------------------------------ r zcd ? =
application information ALTAIR04-900 16/29 doc id 18211 rev 2 5.5 constant current operation figure 14 presents the principle us ed for controlling the averag e output curr ent of the flyback converter. the output voltage of the auxiliary winding is used by the demagnetizat ion block to generate the control signal for the mosfet switch q1. a resistor r in series with it absorbs a current v c /r, where v c is the voltage developed across the capacitor cref. the flip-flop?s output is high as long as the transformer delivers current on secondary side. this is shown in figure 15 . the capacitor cref has to be chosen so that its voltage v c can be considered as a constant. since it is charged and discharge by currents in the range of some ten a (i cref is typically 20 a) at the switching frequency rate, a capacitance value in the range 4.7-10 nf is suited for switching frequencies in the ten khz. the average output current can be expressed as: where n pri is the primary turn's number. this formula shows that the average output current does not depend anymore on the input or the output voltage, neither on transformer inductance values. the external parameters defining the output current are the transformer ratio n and the sense resistor r sense . current loop gain g i and current reference voltage v cref are internally defined. figure 14. current control principle (2) i out n pri n sec ------------- - g i v cref ? 2r sense ? () -------------------------------- - ? = ? . iref rzcd rfb aux q1 ir ef r gi demag logi c to pwm logic from rsense zcd/ fb + - cc c s r q
ALTAIR04-900 application information doc id 18211 rev 2 17/29 figure 15. constant current operation: switching cycle waveforms 5.6 voltage feedforward block the current control structure uses the voltage v c to define the output current, according to (2). actually, the cc comparator is affected by an internal propagation delay td, which switches off the mosfet with a peak current than higher the foreseen value. this current overshoot is equal to: where lp is the primary inductance and it introduces an error on the calculated cc setpoint, depending on the input voltage. the device implements a line feedforward function, which solves the issue by introducing an input voltage dependent offset on the current sense signal, in order to adjust the cycle-by- cycle current limitation. the internal schematic is shown in figure 16 . t t t t i p i s q i c t r v i c cref ? = cref i (3) in d p p vt i l ? =
application information ALTAIR04-900 18/29 doc id 18211 rev 2 figure 16. feedforward compensation: internal schematic the r zcd resistor can be calculated as follows: in this case the peak drain current does not depend on input voltage anymore. one more consideration concerns the r zcd value: during mosfet?s on-time, the current sourced by the zcd/fb pin, i zcd , is compared with an internal reference current i zcdon (-50 a typical). if i zcd < i zcdon , the brownout function is activated and the ic is shut-down. this feature is especially important when th e auxiliary winding is a ccidentally disconnected and considerably increases the en d-product?s safety and reliability. 5.7 burst-mode operation at no load or very light load when the voltage at the comp pin falls 65 mv below a threshold fixed internally at a value, v compbm , the ic is disabled with the mosfet kept in off state and its consumption reduced at a lower value to minimize vcc capacitor discharge. in this condition the converter operates in burst-mode (one pulse train every t start = 500 s), with minimum energy transfer. as a result of the energy delivery stop, the output voltage decreases: after 500 s the controller switches-on the mosfet again and the sampled voltage on the zcd pin is compared with the internal reference. if the voltage on the ea output, as a result of the comparison, exceeds the v compl threshold, the device restarts switching, otherwise it stays off for another 500 s period. in this way the converter works in burst-mode with a nearly constant peak current defined by the internal disable level. then a load decrease causes a frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulation s. this kind of operation, shown in the timing ? . cc block aux r zcd rfb iff rsense rff + - cc feedforward logic pwm logi c zcd/ fb drain source (4) aux p ff zcd pri d sense nlr r ntr ? =? ?
ALTAIR04-900 application information doc id 18211 rev 2 19/29 diagrams of figure 17 along with the others previously described, is noise-free since the peak current is low figure 17. load-dependent operating modes: timing diagrams 5.8 soft-start and starter block the soft start feature is automatically implemented by the constant current block, as the primary peak current is limited from the voltage on the c ref capacitor. during start-up, as the output voltage is zero, the ic starts in cc mode with no high peak current operations. in this way the voltage on the output capacitor increases slowly and the soft-start feature is ensured . actually the cref value is not important to define the soft-start time, as its duration depends on others circuit parameters, like transformer ratio, sense resistor, output capacitors and load. the user can define the best appropriate value by experiments . ? co m p i ds 65 mv hyster. normal-mode burst-mode normal-mode t sta r t t start t start t st ar t v compl
application information ALTAIR04-900 20/29 doc id 18211 rev 2 5.9 hiccup mode ocp the device is also protected against short circui t of the secondary rectifier, short circuit on the secondary winding or a hard-saturated flyback transformer. a comparator monitors continuously the voltage on the r sense and activates a protection circuitry if this voltage exceeds 1 v. to distinguish an actual malfunction from a disturbance (e.g. induced during esd tests), the first time the comparator is tripped the protection circuit enters a ?warning state?. if in the subsequent switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protec tion logic will be reset in its idle state; if the com parator is tripped again a real malfunction is assumed and the device is stopped. this condition is latched as long as the device is supplied. while it is disabled, however, no energy is coming from the self-supply circuit; hence the voltage on the v cc capacitor decays and cross the uvlo threshold after some time, which clears the latch. the internal start-up generator is still off, then the v cc voltage still needs to go below its restart volt age before the v cc capacitor is charged again and the device restarted. ultimately, this results in a low- frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. this special condition is illustrated in the timing diagram of figure 18 . figure 18. hiccup-mode ocp: timing diagram ? v ds vc c on vc c of f vcc rest secondary diode is shorted here t t t v source 1 v two switching cycles v cc vcs dis
ALTAIR04-900 application information doc id 18211 rev 2 21/29 5.10 layout recommendations a proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is true for the ALTAIR04-900 as well. careful component placing, correct traces routing, appropriate traces widths and compliance with isolation distances are the major issues. in particular: the compensation network should be connected as close as possible to the comp pin, maintaining the trace for the gnd as short as possible signal ground should be routed separately from power ground, as well from the sense resistor trace. figure 19. suggested routing for converter ? a c i n ou t gnd comp sou rce dr ai n vd d iref gn d fb/ zc d a ltair04-90 0 a c i n
typical application ALTAIR04-900 22/29 doc id 18211 rev 2 6 typical application figure 20. test board schematic: 4.5 w (9 v - 500 ma) wide range mains adapter figure 21. electrical schematic for 440 vac input voltage option thanks to the 900 v rated power section of ALTAIR04-900 &4 5 . & x) / x) %5 5 n & q) 5 n & x) 9 7 & x ) & ) 5 . ' 6736/ 5 5 . & x) 9 ' 1 & x) & q) & q) <& $3 5 : & q) & q) & q) ' 677+ / 5 n 5 / x+ 9 ( & 5 8 2 6 3 0 2 & '5 $,1 9'' &855(17 &21 752/ ,5() *1 ' )%=&' 8 $/7$,5 *1' $&,1 $&,1 9$ *1' 6736/$ ' & q) 75 1& 5 q) < &$3 & . 5 ' 3.($ ) $ 59 9 & q) ; p+ / 9 &203 6285& ( '5 $,1 9'' &855 (17 &21752/ ,5 () *1' )%=& ' 8 $/7 $,5 5 . 5 677+ ' & q) & x) . 5 3' '%/6*5' n 5 & x) 9 6736 ' 9$ & q) & q) $&, 1 & x) $&, 1 ' 6736 5 & x) 1& 5 n 5 &0 / x+ q) & x) & ,1 *1' 287 4 /)$% x) & 9$ & q) ; & x) 9 17& rkp : 5 0 5 0 17& rkp :
ALTAIR04-900 typical application doc id 18211 rev 2 23/29 6.1 test board: evaluation data figure 22. no-load consumption figure 23. efficiency at full load 100 150 200 250 300 350 400 0 20 40 60 80 100 input power [mw] dc input voltage [v] 50 100 150 200 250 300 50 60 70 80 90 10 0 eff iciency [%] ac in p u t vo l ta g e [ v ac ] figure 24. vi curve @ 110 v ac figure 25. vi curve @ 264 v ac 0 100 200 300 400 500 6 7 8 9 10 11 12 output voltage [v] output current [ma] 0 100 200 300 400 500 6 7 8 9 10 11 12 output voltage [v] output current [ma]
typical application ALTAIR04-900 24/29 doc id 18211 rev 2 6.2 test board: main waveforms figure 26. 110 v ac , no-load figure 27. 264 v ac , no-load m: 400 s/div m: 400 s/div figure 28. 110 v ac , full load figure 29. 234 v ac , full load m: 400 s/div m: 400 s/div
ALTAIR04-900 package mechanical data doc id 18211 rev 2 25/29 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 5. so16n mechanical data dim. mm inch min typ max min typ max a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45 (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4.0 0.150 0.157 g 4.60 5.30 0.181 0.208 l 0.4 1.27 0.150 0.050 m 0.62 0.024 s 8 (max.)
package mechanical data ALTAIR04-900 26/29 doc id 18211 rev 2 figure 30. package dimensions
ALTAIR04-900 order codes doc id 18211 rev 2 27/29 8 order codes table 6. ordering information order code package packaging ALTAIR04-900 so16n tu b e ALTAIR04-900tr tape and reel
revision history ALTAIR04-900 28/29 doc id 18211 rev 2 9 revision history table 7. document revision history date revision changes 11-nov-2010 1 initial release 25-jan-2011 2 updated chapter table 4. on page 7
ALTAIR04-900 doc id 18211 rev 2 29/29 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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